Dallas IEEE CS Meeting -- 15 JUN 2007

IEEE Computer Society

Dallas Chapter

15 JUN 2007 Meeting

*When:*	Friday 15 JUN 2007 Lunch: 11:30 AM - 12:15 PM Talk: 12:15 PM - 1:00 PM
*Where:*	Texas Instruments ("South Campus") 12500 TI Boulevard (SAME location as 8505 Forest Ln; just redefined main gate) Dallas, TX (Conference Rooms S1 & S2)
*Topic:*	On-Chip Instrumentation and In-Silicon Debug Tools for SoC ( .pdf )
*Speaker:*	Dr. Neal Stollon Director of OCI Technical Marketing MIPS Technologies
*Abstract:*	On-chip or “in silicon” instrumentation refers to different types of silicon IP and supporting tools and probes used to increase on-chip visibility and control of SoC operations, and to provide a variety of event monitoring, triggering, and trace capabilities at different levels in an architecture. On-chip instrumentation is an increasingly important consideration in SoC design, due to its role in allowing in-depth and real time systems and software debug, verification, and analysis of SoCs and in improving time to market for release of silicon products. On-chip instruments can include a range of solutions and approaches, developed in house or by IP venders, that address various embedded processor and inter-processor analysis for complex systems as well as a range of IO interfaces for on-chip/off-chip communication. There is an increasing amount of activity looking into standardization of the interfaces, features, and methodologies related to on chip debug. This talk provides an overview into the technical aspects, alternatives, and considerations for on-chip debug and addresses their overlap and interactions, especially as they apply to multi-core architectures. We summarize by discussing open issues and standards efforts and coordination needed for next-generation on-chip instrumentation and debug environments.
*Bio:*	Dr. Neal Stollon is a systems and technical marketing engineer focused on system level on-chip instrumentation solutions. He is currently director of Technical Marketing for On-Chip Instrumentation at MIPS Technologies. He has over 25 years of digital design and processor development experience at MIPS Technologies, LSI Logic, Alcatel, Texas Instruments, and others. He has been active in several of the debug related activities being discussed. Dr. Stollon has a Ph.D in EE from SMU, is a Texas Professional Engineer, has written over 35 technical papers, holds 10 patents, and is a Senior Member of IEEE.
*Directions:*	Even though TI's Forest Lane site has been given a new official entrance address at 12500 TI Boulevard and been renamed as TI's "South Campus," find our Dallas IEEE CS meetings just as you've always done. Head to the site's SouthEast (SE) entrance off Forest Lane JUST west of Greenville Avenue. Preferred parking is at extreme SE corner of the building. Enter the public lobby at building's SE corner and ask guard to direct you to conference rooms S-1/S-2 (very near this entrance). (See map.)
*Cost:*	Technical Presentation: FREE to both IEEE CS Members and the general public. Lunch: $10 to both Members and Non-Members. Please reserve lunch by 11 JUN with our online form or by contacting Lucrecia at 214-480-4194 (Lucrecia) .
*Access:*	Since the meeting rooms are inside TI, some attendees may need to pre-register for access. If you are neither a U.S. citizen nor permanent U.S. resident (with "green card") and are from a "restricted country", please contact Jim at 214-480-4691 (Jim) by 11 JUN to arrange for convenient pre-registration .

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